1. Field of the Invention
The present invention relates to a bottom lead package for a semiconductor chip, and in particular to a stackable type bottom lead package.
2. Background of the Related Art
Bottom lead packages, which are a type of semiconductor chip package, are increasingly used in the industry. Such bottom lead packages are classified into two types based on a chip pad formation position. One type is a Side Pad-Bottom Lead Package (S-BLP) in which chip pads are disposed on an upper edge portion of the chip. The other type is a Center Pad-Bottom Lead Package (C-BLP) in which chip pads are disposed on an upper center portion of the chip.
The related art bottom lead packages will now be explained in more detail with reference to FIGS. 1-4.
FIG. 1 illustrates an S-BLP. As shown therein, the S-BLP includes a semiconductor chip 1, and a plurality of upwardly bent leads 3 which are attached to the lower sides of the chip 1 by an adhesive 2. Metal wires 4 electrically connect a plurality of chip pads la formed on the sides of the upper surface of the chip 1 to the leads 3, and a molding section 5 encapsulates the chip 1, the metal wires 4, and the leads 3 with an epoxy such that lower surfaces of the leads 3 are externally exposed.
To mount an S-BLP 6 on a printed circuit board (PCB), a solder mask is disposed on the upper surface of a printed circuit board (PCB) 7, and a solder paste 8 is screen-printed on the upper surface thereof. The solder paste 8 is applied to the upper surfaces of lands 7a disposed on the upper surface of the PCB 7. The S-BLP 6 is then positioned on the PCB 7 so that the exposed portions of the leads 3 of the S-BLP 6 are aligned with the upper surfaces of the corresponding lands 7a. The resultant structure then undergoes a reflow process to attach the lower surfaces of the leads 3 to the PCB 7, as shown in FIG. 2.
FIG. 3 illustrates the structure of a C-BLP. As shown therein, the C-BLP includes a semiconductor chip 11, and a plurality of leads 13 attached to the upper sides of the chip 11 by an adhesive 12. Metal wires 14 electrically connect the leads 13 and a plurality of pads 11a formed on the upper center of the chip 11, and a molding section 15 encapsulates the chip 11, the metal wires 14, and the leads 13 such that the upper surfaces of the leads 13 are partially exposed.
As shown in FIG. 4, to mount the C-BLP on a printed circuit board, a solder paste 18 is applied to the upper surfaces of lands 17a formed on the upper surface of the PCB 17. Thereafter, the C-BLP 16 shown in FIG. 3 is inverted, and the leads 13 are aligned with the upper surfaces of the lands 17a. The resultant structure then undergoes a reflow process to attach the leads 13 to the PCB 17, as shown in FIG. 4.
In these types of bottom lead packages, since the exposed surfaces of the leads 3 and 13 are formed on only one side of the package, the packages cannot be stacked to increase the capacity of a package semiconductor memory device.